| Many current and future
programs are pushing computers to the limits, calling for faster
processors, memory, graphics, networks and storage; all of which requires
faster interconnects. The PCI bus has served us well, ushering numerous
I/O devices over the last decade. However, the time is finally coming to
replace this old standard with a newer and faster protocol. It is already
possible for an ATA 133 hard drive to overload the bandwidth of the PCI
bus. Now lets think about RAID, SCSI and even Gigabit Ethernet.
Example of current PCI
architecture. Look at the various data busses used.
During the last few years numerous standards have been developed to offset
the aging PCIs ability to offer bandwidth to devices. AGP, HyperTransport,
ATA, and USB are just a few of the protocols that have been thought up to
replace PCI. Intel, realizing this problem, spearheaded an organization to
develop a standard that would revolutionize the way computers could be
made, while solving their bandwidth problem as well. Soon, Microsoft, IBM,
Dell, and Compaq were all aboard the PCI-Express bandwagon. A major
victory for the budding standard came when AMD, already developing a
similar technology called HyperTransport, finally signed on.
PCI Express, (also known as Third
Generation I/O, 3GIO, and Arapahoe) should allow us to have more than
adequate bandwidth for another decade. Unlike its older cousin, PCI-Express
is a fully serial interface, rather than the parallel bus architecture
found in the current PCI bus. It can be used for many functions, including
universal connectivity for use as a chip-to-chip interconnect, I/O
interconnect for adapter cards, an I/O attach point to other
interconnects. PCI Express can provide I/O attach points for
high-performance graphics, 1394b, USB 2.0, InfiniBand Architecture,
Gigabit networking and many other bandwidth hungry architectures.
On July 23, 2002, the PCI-SIG approved
PCI-Express 1.0. Here is a brief spec-sheet of the initial standard.
PCI software compatibility
Scalable performance for multiple computing and communications market
segments
Suitable for chip-to-chip, board-to-board, add-in peripherals and
backplane implementations
Support for end-to-end data integrity to achieve highly-available
solutions
Advanced error reporting and handling for fault isolation and system
recovery
Native power management functions for flexible platform power budgeting
Inherent hot plug and hot swap capabilities with compatible support for
existing PCI hot-plug schemes
Low-overhead, low-latency data transfers and maximized interconnect
efficiency
Differentiated services through isochronous data delivery for
bandwidth-sensitive applications
Multi-hierarchy and advanced peer-to-peer communications across fabric
topologies
High-bandwidth, low pin-count implementations for optimized performance
Cost effective silicon component designs relative to package and
die-area
PCI-Express
Roadmap
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